Source-synchronous communications links use a clock signal to synchronise data transmission and data reception. For example, the clock signal used for data transmission is provided over a clock line to the reception circuit such that the data reception can be based on a common clock signal. Such a solution is relatively robust against propagation delay variations over the communications link, as the propagation delays of the data streams and of the clock signal will remain substantially equal.
However, for source-synchronous links operating at relatively high data rates, the relative timing of the received clock and data signals may become non-optimal, potentially leading to an increase in the rate of data reception errors. One solution to this problem involves detecting and correcting errors in the received data signal based on error correcting code, and adjusting the relative timing of the data and clock signals in order to reduce to a minimum the error rate. However, such a solution is relatively complex and consuming in terms of chip area and power consumption. Therefore, such a solution is generally not justified for communications over relatively short distances, and/or for parallel data interfaces where the error rate of each date line needs to be considered.
There is thus a need for a simple and effective circuit and method for ensuring correct synchronization of a source-synchronous communications link.